1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same. More particularly, the invention relates to a void-free semiconductor device and a method of fabricating the same.
2. Description of Related Art
With the continual miniaturization of semiconductor devices, dimensions of gate structures are also gradually reduced. Therefore, the thickness of gate dielectric layers also needs to be reduced to prevent the performance of the devices from being affected. Generally, the material of the gate dielectric layers usually includes silicon oxide. However, the leakage current phenomenon frequently occurs when reducing the thickness of the gate dielectric layers adopting silicon oxide. In order to reduce the occurrence of leakage current, a conventional method is to replace silicon oxide with high dielectric constant (high-k) material for the gate dielectric layers. When applying high dielectric constant material in the gate dielectric layers, the gates adopting polysilicon then react with high dielectric constant material to generate Fermi-level pinning, thereby resulting in an increase in the threshold voltage so as to affect device performance. In one of the conventional techniques, the metal layer is applied as the gate, that is, the work function metal layer known in the art, to prevent the threshold voltage from increasing and therefore reducing the resistance of the device.
In a conventional gate structure composed of a high dielectric constant dielectric layer and a metal gate, the dummy patterns are first formed and then the gate structures are formed in the current method. In other words, the dummy patterns and the interlayer dielectric layer are first formed on the substrate. Next, the dummy patterns are removed, and then the metal gate structures are formed in the openings that are formed after the removal of the dummy patterns.
However, in the process of patterning the dummy pattern material layer to form the dummy patterns, due to the constraints of the etching process, the resultant dummy patterns are usually shaped into trapezoids having a narrow top and a wide bottom, so that an included angle between the top sidewall of each the dummy pattern and the surface of the interlayer dielectric layer is about 88°-89°. Since the trapezoid dummy patterns have a narrow top and a wide bottom, an opening with a narrower top portion is formed after the dummy patterns are removed. Hence, when the opening is filled with the metal layer by a sputtering process, the effect of metal gap fill is poor, so that problems such as overhang and the like usually occur to cause the formation of voids in the metal layer, thereby affecting the reliability and performance of the device.